After practically a decade and 5 main nodes, together with a slew of half-nodes, the semiconductor manufacturing trade will start transitioning from finFETs to gate-all-around stacked nanosheet transistor architectures on the 3nm know-how node.

Relative to finFETs, nanosheet transistors ship extra drive present by rising channel widths in the identical circuit footprint. The gate-all-around design improves channel management and minimizes short-channel results.

 

Fig. 1: In nanosheet transistors, the gate contacts the channel on all sides (gate all around) and multiple sheets enable higher drive current than in finFETs in the same footprint. Silicon orientation differences (110 to 100) changes the carrier mobilities in the channel. Source: K. Zhao, IEEE IEDM 2021

Fig. 1: In nanosheet transistors, the gate contacts the channel on all sides (gate throughout) and a number of sheets allow larger drive present than in finFETs in the identical footprint. Silicon orientation variations (110 to 100) modifications the service mobilities within the channel. Supply: Okay. Zhao, IEEE IEDM 2021

Superficially, nanosheet transistors resemble finFETs, however nanosheet channels are aligned parallel, not perpendicular, to the substrate. Nanosheet transistor fabrication begins with deposition of a Si/SiGe heterostructure, remoted from the substrate to stop parasitic conduction.

A primary patterning step cuts this heterostructure into pillars. After dummy gate fabrication, an inside spacer etch step cuts a recess within the SiGe layers. The inside spacer etch step (mentioned in additional element under) is a important course of step, as a result of it defines the gate size and the supply/drain junction overlaps. As soon as the inside spacer is in place, supply/drain epitaxy, a channel launch etch, and formation of the substitute gate full the transistor.

Constructing transistor pillars
Despite the fact that the SiGe layers are sacrificial materials — not a part of the completed machine — their germanium focus is a crucial course of variable. As Nicolas Loubet and colleagues at IBM and TEL defined in work introduced on the 2019 IEEE Electron Gadget Assembly, rising the quantity of germanium will increase the SiGe lattice fixed, which in flip will increase lattice pressure within the silicon layers, probably introducing defects.[1] Alternatively, utterly eradicating the SiGe materials with out damaging or eroding the silicon requires an etching course of with excessive SiGe:Si selectivity. Decreasing the germanium focus tends to scale back selectivity.

Ideally, machine designers wish to decrease the spacing between nanosheets to be able to cut back parasitic capacitances. There are sensible limits to the manufacturable spacing, although, as IBM researcher Kai Zhao defined in a tutorial session ultimately 12 months’s IEDM. As soon as the sacrificial SiGe is gone, the area between nanosheets must accommodate residue elimination, the gate steel, the gate dielectric, and (particularly for pFETs) any further work perform adjustment layers.

After Si/SiGe heterostructure deposition, an anisotropic etch cuts pillars of the specified width. In finFET architectures, fin width is standardized, partly because of the limitations of lithography schemes that rely on pitch-doubling. The adoption of utmost ultraviolet lithography offers designers extra flexibility to make use of variable machine widths as wanted.

Naoto Horiguchi, imec’s director of CMOS machine know-how, defined in an interview that nanosheet transistor pillars might be wider than finFET fins. Additional, the width of a stacked nanosheet transistor is the sum of its element nanosheets. Because of this, the variability of the pillar width is usually small relative to the overall channel width.

Fig. 2: The etch profile directly affects transistor behavior and consistency in device operation. Source: IBM Research

Fig. 2: The etch profile immediately impacts transistor conduct and consistency in machine operation. Supply: IBM Analysis

As a result of Si and SiGe have totally different etch traits, etching via alternating Si/SiGe layers is a extra advanced activity than etching a monolithic silicon pillar. Eric Miller, supervisor for plasma etch analysis at IBM Analysis, defined that electrically, every layer in a stacked nanosheet machine capabilities as an unbiased transistor. If the etch profile of the stack just isn’t vertical, the size and traits of the element units will differ.

Additional, Horiguchi famous that, as when etching silicon, the method must stability etching and sidewall passivation. Uncovered SiGe surfaces are typically much less secure than silicon.

Defining the channel
As soon as the nanosheet pillars are outlined, a extremely selective isotropic etch creates the inside spacer recess, indenting the SiGe layers relative to the silicon nanosheets. This spacer defines the gate size and junction overlap, Loubet mentioned, each of that are important transistor parameters that assist outline the tradeoff between machine resistance and capacitance. The form of the indentation defines the separation between the remaining SiGe — which finally will probably be changed by the gate — and the supply/drain areas. Moist chemistry etch processes have a tendency to depart half-moon profiles, as a meniscus kinds between two adjoining nanosheets. Elimination of the remaining SiGe in the course of the channel launch etch can expose the supply/drain and place them in direct contact with the gate steel.

Fig. 3: Critical etching steps in the nanosheet transistor process flow include dummy gate etch, anisotropic pillar etch (b), isotropic spacer inner space etch (c) and the channel release step (g). Source: N. Loubet, IBM

Fig. 3: Important etching steps within the nanosheet transistor course of stream embody dummy gate etch, anisotropic pillar etch (b), isotropic spacer inside area etch (c), and the channel launch step (g). Supply: N. Loubet, IBM

Whereas dry etch processes go away no meniscus, Yu Zhao and colleagues at Hitachi nonetheless noticed a rounded etch entrance. In work introduced ultimately 12 months’s IEEE Electron Gadgets Know-how and Manufacturing Convention (EDTM), Hitachi researchers used STEM-EDX to measure germanium focus, figuring out a germanium-rich layer on the sidewalls of their Si/SiGe pillars. The layer, which apparently fashioned in the course of the anisotropic pillar etch, etched extra rapidly, resulting in a rounded etch entrance. Then, because the etch proceeded via this sidewall area into the majority SiGe materials, with a uniform germanium focus, the uniform etch fee preserved the present etch entrance form. Additional optimization of the pillar etch resolved the issue.[2]

The final new course of module in nanosheet units, the channel launch etch, defines the ultimate nanosheet thickness. Whereas the semiconductor trade may be very able to depositing exactly managed and uniform heterostructures, sustaining such exact management whereas etching the SiGe away presents some new challenges. Constant transistor efficiency requires extraordinarily uniform nanosheets, Loubet mentioned, usually with 0.5nm or much less of silicon loss.

EUV lithography permits designers to specify variable machine widths, however they depend on the channel launch etch to truly obtain them. If the channel launch etch just isn’t selective sufficient, the silicon nanosheets in slim units will erode earlier than the channels in wider units are cleared. As a result of etch selectivity relies on germanium focus, germanium residue and germanium diffusion in the course of the pillar or inside spacer etch can result in silicon loss in the course of the channel launch etch.

Shifting past nanosheets
Whilst the primary nanosheet units make their method to manufacturing, producers are already contemplating enhancements for future scaling. Imec’s forksheet design, as an example, locations an insulating pillar between the n-channel and p-channel halves of an nFET/pFET pair. The improved isolation reduces the minimal spacing between the 2, and due to this fact the general circuit footprint.

IBM’s Kai Zhao famous that distinctive machine mobility issues come up as a result of the nanosheet structure locations the (100) crystal airplane parallel to the substrate, versus the (110)-oriented channel in finFETs. Utilizing the (100) airplane modifications each absolutely the and relative mobilities of electrons and holes.

Table 1: Carrier mobilities in silicon finFETs and nanosheet FETs. Source: Kai Zhao, IBM/IEDM Tutorial, 2021

Desk 1: Provider mobilities in silicon finFETs and nanosheet FETs. Supply: Kai Zhao, IBM/IEDM Tutorial, 2021

One proposal to enhance gap mobility, described by R. Bao and colleagues at IBM ultimately 12 months’s IEDM, makes use of silicon channels for nFETs and SiGe pFET channels. The nFET nanosheet stack alternates silicon and SiGe, whereas the pFET stack makes use of SiGe channel layers with SiGe sacrificial layers. Separation between the 2 relies on the germanium sensitivity of the etch course of.[3]

An alternate strategy, demonstrated by Wei-Yuan Chang and colleagues at Taiwan Semiconductor Analysis Institute, depends on Si/SiGe stacks for each nFET and pFET units. On this strategy, a combination of hydrofluoric acid, hydrogen peroxide, and acetic acid removes SiGe from stacks destined to change into nFETs, attaining a selectivity of about 79:1. TMAH answer was used to take away silicon from stacks that may change into pFETs, attaining about 8:1 selectivity. These early outcomes have been promising, they mentioned, however additional optimization of the pFET etch is required.[4]

Additional scaling of nanosheet transistors would require much more drive present in the identical or smaller circuit footprint. To that finish, Sylvain Barraud and colleagues at Leti demonstrated each nFET and pFET units with seven silicon channels, as an alternative of the extra typical two, tripling the out there drive present.[5] Even additional sooner or later, doable designs embody complementary FETs (CFETs), wherein a single nanosheet stack accommodates each p-type and n-type channels, and vertical transport nanosheet FETs (VTFETs), with nanosheets perpendicular to the substrate airplane.

Regardless of the future holds, it’s clear that the trade is in no hurry to desert silicon, regardless of the theoretical benefits of other supplies.

References

  1. N. Loubet et al., “A Novel Dry Selective Etch of SiGe for the Enablement of Excessive Efficiency Logic Stacked Gate-All-Round NanoSheet Gadgets,” 2019 IEEE Worldwide Electron Gadgets Assembly (IEDM), 2019, pp. 11.4.1-11.4.4, doi: 10.1109/IEDM19573.2019.8993615.
  2. Y. Zhao, T. Iwase, M. Satake and H. Hamamura, “Formation Mechanism of a Rounded SiGe-Etch-Entrance in an Isotropic Dry SiGe Etch Course of for Gate-All-Round (GAA)-FETs,” 2021 fifth IEEE Electron Gadgets Know-how & Manufacturing Convention (EDTM), 2021, pp. 1-3, doi: 10.1109/EDTM50988.2021.9421041.
  3. R. Bao et al., “Important Parts for Subsequent Technology Excessive Efficiency Computing Nanosheet Know-how,” 2021 IEEE Worldwide Electron Gadgets Assembly (IEDM), 2021, pp. 26.3.1-26.3.4, doi: 10.1109/IEDM19574.2021.9720601.
  4. W. -Y. Chang et al., “SiGe and Si Gate-All-Round FET Fabricated by Selective Etching the Similar Epitaxial Layers,” 2022 sixth IEEE Electron Gadgets Know-how & Manufacturing Convention (EDTM), 2022, pp. 21-23, doi: 10.1109/EDTM53872.2022.9797991.
  5. S. Barraud et al., “7-Ranges-Stacked Nanosheet GAA Transistors for Excessive Efficiency Computing,” 2020 IEEE Symposium on VLSI Know-how, 2020, pp. 1-2, doi: 10.1109/VLSITechnology18217.2020.9265025.

Associated Studying
Transistors Reach Tipping Point At 3nm
Nanosheets are likeliest possibility all through this decade, with CFETs and different unique constructions doable after that.

Stacked Nanosheet And Forksheet FETs
Subsequent-gen transistors will proceed utilizing silicon, however gate constructions and processes will change.

New Transistor Structures at 2nm/3nm
Gate-all-around FETs will change finFETs, however the transition will probably be expensive and tough.



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