Wafer cleansing, as soon as a slightly mundane process so simple as dipping wafers in cleansing fluid, is rising as one of many prime main engineering challenges for manufacturing GAA FETs and 3D-ICs.

With these new 3D constructions — some on the horizon however some already in high-volume manufacturing — semiconductor wafer tools and supplies suppliers within the moist cleansing enterprise are on the epicenter of a push for elevated yield and reliability. Cleansing logic and reminiscence constructions was once easy. However beginning with finFETs, and transferring subsequent into gate-all-around (GAA) constructions, in addition to superior DRAM capacitors and 3D NAND, cleansing has entered a 3rd — and never at all times seen nor measurable — dimension.

Cleansing steps are discovered all through the semiconductor manufacturing course of, and there are a whole lot of them. They contain not simply cleansing, however ensuring the floor is ready for the following step in photoresist, post-etch and implant strip, basic cleansing, and bottom cleansing for a number of patterning and EUV, notes Sally-Ann Henry, director of enterprise improvement at ACM Analysis. What was as soon as a shower in a moist bench has advanced into modern single-wafer cleansing options for the superior nodes.

“As new supplies and course of architectures are launched into an already advanced manufacturing course of, a specialised cleansing course of is the important thing to additional innovation,” stated Brian Wilbur, director, Semiconductor Merchandise Diversification at Brewer Science. He described the corporate’s custom-made strategy to cleansing. For example, Brewer’s selective floor modification supplies can present excessive selectivity to metals, polymers, dielectrics, and so on., to boost cleansing options.

“As scaling continues, options are getting smaller and extra advanced, and chipmakers are exploring new supplies. That is making attaining exact, uniform cleansing more difficult,” stated David Kretz, senior director of key account expertise for Lam Analysis’s Clear Product Line. “New approaches are wanted for superior next-generation logic, DRAM, and NAND. As cleansing processes are additionally used a number of instances within the chip-making course of to take away yield-limiting residue and defects, the necessity for cost-effective, extremely environment friendly processes is even better.”

The marketplace for Moist Wafer Processing Techniques is barely greater than $5B, in response to TechInsights. The highest three corporations — so as: Display, TEL and Lam — account for about 75% of the market. The subsequent three — Semes, Naura, and ACM Analysis — account for an additional 20%. Regardless of the dominance of the highest three, Risto Puhakka, president of VLSI Analysis (now a part of TechInsights), describes {the marketplace} as “pretty aggressive.” Like a lot of the tools market, the moist clear tools market noticed huge upswings during the last couple of years, reaching progress of greater than 40% in 2021. The agency sees it dropping to -7% in 2023, however selecting up once more with an AAGR in 2022 to 2027 of 8.3%.

Fig. 1: The EOS wet clean system delivers low on-wafer defectivity and high throughput to address demanding wafer cleaning applications. Source: Lam Research

Fig. 1: The EOS moist clear system delivers low on-wafer defectivity and excessive throughput to handle demanding wafer cleansing purposes. Supply: Lam Analysis

3D constructions
The challenges are considerably completely different for logic versus reminiscence constructions. At Semicon West 2022, Ian Brown, vice chairman, engineering at Display, gave an in depth speak entitled, “Distinctive Challenges Related to Manufacturing 3D Units and Constructions Together with GAA, 3D DRAM, and 3D NAND and Wafer Cleansing Know-how in 3D Built-in Circuit Units.” (The video is on the market here.)

Think about logic units. Whereas cleansing for finFETs in high-volume manufacturing now not presents any explicit difficulties, the upcoming transfer to GAA constructions — first nanosheets and later forksheets — is rife with challenges.

“The large problem is the hidden surfaces,” stated Brown. “How do I clear etch a floor I can not see?” The confined, hidden vertical surfaces are particularly robust. In nanosheets, six vertical surfaces are hidden, and in forksheet FETs that quantity rises to sixteen.

New supplies are also being added, which increase problems for selectivity. The trade is new moist chemistry choices, vapor etch, or some mixture therein.

However with the arrival of nanosheets, Brown stated the brand new consideration is sample collapse. This phenomena was encountered beforehand with 3D NAND, so a few of that studying will be utilized to the brand new logic constructions.

Fig. 2: New logic structures will require new cleaning solutions. Source: Screen Semiconductor/SEMI

Fig. 2: New logic constructions would require new cleansing options. Supply: Display Semiconductor/SEMI

In reminiscence constructions, each 3D NAND and deep DRAM capacitors current challenges. In 3D NAND, the variety of cell layers retains growing. Micron not too long ago introduced it has reached 232 layers. That makes etching uniformity down the pillars very important. “You recognize, it’s very simple to over-etch this stuff since you’re focusing on a uniform edge prime to backside,” Brown noticed. “And the efficiency of those units requires a uniform edge within the vertical course.”

A number of work has been carried out during the last 5 years, however this stays tough. “As a part of the scaling of 3D NAND, the facet ratio of those horizontal traces is getting more difficult,” he stated. “And even in the present day, we have now sample collapse within the horizontal course.

Whereas the trade has lengthy handled vertical sample collapse, the problem is now the facet ratio within the horizontal course. The trade is engaged on fixing that downside to convey this expertise into high-volume manufacturing.

Fig. 3: 3D NAND poses new cleaning challenges. Source: Screen/SEMI

Fig. 3: 3D NAND poses new cleansing challenges. Supply: Display/SEMI

Defect removing
Defect removing was as soon as only a case of etching the floor and soaking the wafers in a moist bench tub, releasing the particles so that they floated away. That cost-effective strategy labored as much as round 90nm, and it had extraordinarily excessive throughput. Nevertheless, after 90nm, different options had been additionally wanted. Wafers had been cleaned individually utilizing a dual-fluid spray system. As particles turned smaller, extra dispersed, and tougher to detach, the spray strain was elevated. However that solely will go thus far earlier than the spray strain causes structural injury.

Moreover, the tiny spray droplets are nonetheless a few micron in dimension — usually twice the dimensions of the trenches they should clear in superior 3D constructions. And with GAA constructions, there isn’t any line of sight, so the sprays can’t even entry hidden surfaces.

Researchers within the trade at the moment are polymers to assist take away particles. A polymer movie is spun on after which peeled off away in a structured trend, taking particles with it. Display’s model of that is known as Nanolift.

Bottom wafer contamination and wafer warping even have change into basic points in superior expertise nodes. Particles left on the again of the wafer can throw off lithography.


Fig. 4: The SB-3300 single-wafer backside cleaning system. Through a combination of a spray and brush cleaning, the tool mechanically removes backside contaminants, precisely etches backside layers and removes wafer edge residues, while minimizing wafer warpage. Source: Screen

Fig. 4: The SB-3300 single-wafer bottom cleansing system. Via a mix of a sprig and brush cleansing, the device mechanically removes bottom contaminants, exactly etches bottom layers and removes wafer edge residues, whereas minimizing wafer warpage. Supply: Display

Previous to 65nm, a well-liked moist cleansing expertise was megasonics, which makes use of very excessive frequency sonic waves to create oscillating bubbles that lightly scrub the construction. However after 65nm, the trade moved away from megasonics, as a result of popping bubbles can injury delicate constructions.

ACM Analysis introduced megasonics again to the fore a couple of years in the past with the introduction of extremely managed bubbles, making it acceptable for the present vary of superior constructions with hard-to-reach areas. The Good Megasonix expertise enable chemical substances to enter deep holes in 3D constructions, adopted by the corporate’s scorching IPA vapor dryer. The success is within the numbers. ACM posted practically 75% year-over-year progress from 2020 to 2021. It’s House Alternated Section Shift (SAPS) expertise employs alternating phases of megasonic waves to ship megasonic power to flat and patterned wafer surfaces in a extremely uniform method on a microscopic degree. The bubbles are allowed to burst, however in a really managed approach, so that they take away random defects throughout the wafer rather more effectively than typical jet spray processes, in response to the corporate.

For much more delicate constructions, ACM’s Well timed Energized Bubble Oscillation (TEBO) expertise permits exact, multi-parameter management of bubble cavitation throughout megasonic cleansing by utilizing a sequence of speedy strain modifications to pressure bubbles to oscillate in particular shapes and sizes. And since these bubbles oscillate however don’t burst, TEBO expertise avoids characteristic injury, making it a very good match for superior 3D constructions and units with very excessive facet ratios.

After every cleansing step, there’s a drying step. In superior 3D constructions, that drying step creates better dangers of sample collapse. In logic, the danger happens in publish STI etch, publish poly etch, nanosheet launch, and nanowire launch. In 3D NAND, the danger of collapse comes throughout the silicon nitride pullback used to create what appears to be like like a “staircase.”

Figure 5. The Cellesta -i MD 300mm single-wafer clean system targets ≤10nm nodes. The system enables thorough cleaning without damage to the well-patterned wafer surface including particle removal. Pattern collapse-free drying technology utilizes chamber atmosphere control and an improved IPA dispenser. Chemical recycling enables higher productivity and lower running cost. Source: TEL

Fig. 5: The Cellesta -i MD 300mm single-wafer clear system targets ≤10nm nodes. The system permits thorough cleansing with out injury to the well-patterned wafer floor together with particle removing. Sample collapse-free drying expertise makes use of chamber environment management and an improved IPA dispenser. Chemical recycling improves permits productiveness and operating value. Supply: TEL

DRAM capacitors are presently the most important problem as a result of aggressive facet ratios.

Whereas spin drying (and a few N2 drying) carried the trade by means of the 2D epoch, the drying of superior 3D constructions now depends on isopropyl alcohol (IPA). Whereas this isn’t a brand new course of, says Brown, with increasingly more IPA drying steps, fabs are confronted with growing unstable natural compound (VOC) emissions. A lot of the cleansing distributors and suppliers at the moment are tackling that in partnership with their clients.

Presently for finFETs, IPA drying is the state-of-the-art. However with extra superior 3D constructions, the floor stress of the liquid can enhance the danger of sample collapse. The subsequent choice is sublimation, which eliminates the liquid part transition altogether by going immediately from a stable to a gasoline.

The subsequent drying choice past sublimation is super-critical carbon dioxide (SC-CO2), wherein the properties of the CO2 are halfway between a gasoline and a liquid. Whereas it’s presently in use by some chipmakers, it’s a comparatively sluggish course of that includes a lot larger strain, power, and use of solvents — all including as much as a lot larger prices. Brown reckons that the continued work to increase IPA drying and sublimation finally will show more cost effective for many HVM.

Etch uniformity
In 2D, uniformity was a query of die-to-wafer or wafer-to-wafer. However in 3D NAND, the uniformity of the etch creates the gate, so the system efficiency may be very strongly depending on etch uniformity. The etch on the prime, center and backside must be uniform. A straight profile is required for the liner and recess metallic. “These are enjoyable issues to work on,” and among the trade’s greatest minds are engaged on it, Brown stated.

There are a couple of approaches to bettering moist etching. The mass transport on the emulsion instruments will be improved, or the change will be produced from immersion instruments to single-wafer instruments. Different alternate options embody vapor etch or a mix of moist and vapor etch. The chemical suppliers are also developing with inventive options so as to add additional management.

To review the controlling of moist chemistry in slim areas, the trade has turned to superior simulation to grasp the basics of the processes.

Environmental issues
Corporations within the cleansing tools and supplies enterprise are on the entrance line of environmental and sustainability issues, so are in search of methods to cut back the chemical and water utilization in addition to the exhaust emissions of their tools.

Figure 6. The Tahoe tool combines batch and single wafer cleaning with optional megasonics in one platform. It can reduce sulfuric acid usage and chemical waste by 80% compared to single wafer systems. Source: ACM Research

Fig. 6: The Tahoe device combines batch and single wafer cleansing with elective megasonics in a single platform. It might probably cut back sulfuric acid utilization and chemical waste by 80% in comparison with single wafer techniques. Supply: ACM Analysis

TEL and Display are amongst people who have joined imec’s Sustainable Semiconductor Technologies and Systems (SSTS) analysis program, which helps the semiconductor trade in lowering its carbon footprint.

All the foremost gamers are in search of methods to cut back sulfuric acid use (one of the vital extensively used chemical substances within the trade), in addition to different chemical substances. Display, for instance, has developed a sulfuric peroxide combination (SPM) reclaim operate on their single-wafer SU-3300 platform, the place the 70% of the dispense quantity of H2SO4 will be reclaimed. It is also focusing on a discount in greenhouse gasoline emissions from using bought merchandise by 20% by 2030.

Chipmakers are also doing their half to lower the environmental footprint of superior construction cleansing processes. UMC, for instance, has been working with chemical suppliers to develop greener, much less poisonous chemical substances, a lot of which have now been deployed of their fabs.

“This may proceed to be difficult as fabrication applied sciences change into more and more advanced, clients’ designs change into extra subtle, and new supplies are launched,” stated Chun-lung Chen, a director in UMC’s Know-how Improvement Module Division who oversees superior improvement of etching and cleansing processes. “Enhancing the effectivity of cleansing solvents and lowering the environmental influence of chemical substances used within the cleansing processes was once seen individually, however the two challenges are converging. Whether or not required by clients, regulatory necessities, or inside ESG targets, the pattern is transferring towards greener options and fewer waste.”

This represents an enormous shift for foundries. “At UMC, we first concentrate on lowering etching waste, or adjusting the residue composition in order that it’s simpler to take away,” he stated. “We then work on optimizing the components, focus, and temperature of solvents with a view to obtain better cleansing effectivity. Extra wafers will be produced utilizing the identical quantity of chemical substances, which brings down prices and generates much less hazardous waste.”

The metrology hole
“For those who can’t measure it, how are you aware how effectively you’re performing?” asks Brown. Attempting new options throughout the improvement course of then having to attend days for a SEM to return again and inform them if they’re heading in the right direction is irritating.

Mark Thirsk, managing associate at Linx Consulting, calls it the metrology hole. “Metrology techniques will not be in a position to measure the contamination ranges and particle sizes which are important,” stated Thirsk, whose firm supplies strategic consulting and market evaluation providers to chemical, gasoline and supplies suppliers within the electronics provide chain. Linx places the “formulated cleans” market — the chemical substances used to take away residues post-etch and post-CMP — at $560 million, with a CAGR of 5% by means of 2025.

A contaminant of just some nanometers gained’t present up on normal in-line metrology tools. It requires a SEM picture to seek out it, which isn’t sensible in a high-volume manufacturing setting, Thirsk famous. “We’re asking the cleansing corporations or the chemical corporations or the tools corporations to regulate past the place we will measure,” he stated. And that’s an issue that’s but to be solved.

For its half, KLA factors to options for figuring out contaminants in unpatterned wafers off-line, however built-in inspection techniques, and chemistry course of management merchandise used to qualify the chemical substances. Nevertheless, says Satya Kurada, vice chairman of promoting at KLA, “KLA works in shut collaboration with our clients and companions throughout the semiconductor ecosystem to grasp their next-generation challenges. This info drives our expertise roadmap, in order that we’re producing merchandise able to addressing chip producers’ most crucial challenges on the proper time.”

Cleansing is important to yield and reliability. New 3D constructions have added many new challenges. Leaders in cleansing applied sciences are engaged on modern options, however some explicit issues, like the dearth of the line-of-sight and the metrology hole, stay unsolved.

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