System-in-package (SiP) is shortly rising because the bundle possibility of alternative for a rising variety of purposes and markets, setting off a frenzy of exercise round new supplies, methodologies, and processes.
SiP is a necessary packaging platform that integrates a number of functionalities onto a single substrate, which allows decrease system price, design flexibility, and superior electrical efficiency by means of shorter interconnections. SiPs are displaying up in 5G, IoT, cellular, shopper, telecom, and automotive apps. Of those, the biggest and maybe most fun section is shopper and wearable packages — from good earbuds to capacitor ache patches — slim, comfy units that quickly ship the well being and health knowledge individuals need.
In lots of respects, SiP and different sorts of advanced packaging allow the efficiency and price advantages as soon as related nearly completely with Moore’s Legislation. “Via our fan-out mixtures, flip-chip, BGA, and embedded options, ASE has labored actually laborious, along with TSMC, to increase the Moore’s Legislation standards the place we hopefully double efficiency — possibly not at half the price, however with a value profit,” mentioned Yin Chang, senior vice chairman of gross sales and advertising at ASE. “That’s why we launched the VIP Platform to offer a toolbox of options that give architects the very best degree of flexibility to create differentiated methods.”
Others agree that superior packaging performs a key position in bettering system efficiency. “On the finish of the day, system-level efficiency is all that issues,” mentioned David Fried, president of Coventor, a part of Lam Analysis. “We’re nonetheless pushing up in opposition to the ability, efficiency, energy, space and price (PPAC) limitations. We’re simply pushing on completely different parameters to maintain enhancing system-level efficiency for so long as the market retains demanding that we offer further compute energy and reminiscence.”
Bundle kind choice sometimes comes right down to balancing efficiency and price. “Flip-chip dominates the RF AiP mmWave market, however there’s a pattern to develop fan-out AiPs (antenna in packages),” mentioned Stefan Chitoraga, know-how and market analyst for Yole Intelligence. “Fan-out benefits embody smaller type issue, leveraging high-density RDL, and wonderful pitch in comparison with flip-chip. However, fan out remains to be too pricey, and there are technical challenges to beat.”
Such challenges embody die shift and warpage, that are being addressed by numerous tooling and course of modifications. 
To allow excessive efficiency, effectivity, and low price in a single SiP, engineers are incorporating new molding supplies, double-sided SiPs, laser-assisted bonding (LAB), and next-generation versatile substrates in fan-out, flip chip, and embedded SiPs.
SiP in 3D
SiP is a part of the trade’s 3D revolution. Together with tendencies to accommodate extra I/Os in finer pitches, there are a selection of different efforts to cram extra right into a bundle somewhat than onto a single die. This contains a number of redistribution layers in fan-outs, bridges and interposers to attach completely different die collectively, double-sided packages to extend density, and embedded die choices to allow quicker die-to die processing in smaller profiles that eat much less energy. “If it weren’t for superior packaging, we’d not have the ability to get the form of chips we have now. It’s actually not simply what’s occurring contained in the chips. It’s how the entire bundle, together with reminiscence and communication, works collectively to make the chips helpful,” mentioned Aki Fujimura, CEO of D2S. “The perfect model of what we will create as a system remains to be this gadget on this substrate and that gadget on that substrate, and individuals are determining the way to mix the most effective efficiency with price effectiveness.”
SiPs immediately mix quite a lot of parts, from GPUs and RF ICs, to recollections, sensors, passives, and far more. “ASE’s SiP know-how helps the combination of various microcontrollers, ASICs, antennas, and sensors that management all of the features in a steady glucose monitor (CGM), for example,” in accordance CP Hung, vice chairman, Company R&D at ASE.
Hung additionally described a redesign of a number of sensors in a quad-flat no-leads (QFN) bundle to a wafer-level chip-scale bundle (WL-CSP) with through-silicon vias, which might enhance electrical efficiency by 80% whereas lowering its footprint by 30%. Hung mentioned there are also biometric purposes for SiP, together with in-vitro diagnostics with microfluidic channels for testing blood, SiP-based listening to aids, and wafer-level SiP for sensor hubs which have a 77% smaller footprint than conventional packaging.
SiPs additionally shake up the availability chain and price constructions. “You see this every single day with cell telephones. They’re getting thinner, lighter, whereas performing extra features, however that requires that the packaging retains tempo with these designs, which implies sustaining sign integrity, managing thermal points, lowering interference, and so on.,” mentioned Sam Sadri, senior course of engineer at QP Technologies. “However the place there are challenges, there are answers. With flip-chip, you attempt to do away with the warmth from the underside if you do die connect, so you utilize a warmth sink and thermal grease on the interface. I’ve seen 3D substrates with piping and coolant working by means of it.”
Along with evaluating all the method and configuration choices inside SiP, Sadri emphasised a rising concern over IP protections in methods.
Fig. 1: The $14B SiP manufacturing market is cut up amongst main OSATs and foundries. Supply: Yole Intelligence
Yole analysts estimate the SiP market will develop at a 5% CAGR to $17 billion in 2025, up from a base of $13.eight billion in 2020 (see determine 1). Market leaders are ASE, Sony, Amkor, JCET, and TSMC. Some 85% of the market is cellular and shopper merchandise, adopted by telecom and infrastructure, then automotive packages.
As well as, SiP I/O pitch is predicted to tighten its vary from 90-350µm immediately to 80-90µm by 2025. “In flip-chip and wire bond SiP, substrate SAP (semi-additive course of) panel is utilized in mixture with embedded silicon bridge utilizing copper pillars, or silicon interposer utilizing TSVs and microbumps,” mentioned Chitoraga.
SiPs encompasses a number of meeting approaches, together with flip-chip and wire bond SiPs (the biggest in income and items), adopted by fan-out WLP, then embedded-die packages. “SiP give system designers the flexibleness to combine and match IC applied sciences, optimize efficiency of every practical block, and cut back price,” mentioned Gabriela Pereira, know-how and market analyst at Yole Intelligence. “Totally built-in SiP options allow designers to implement further functionalities like Bluetooth or digicam modules right into a system with minimal design effort.”
A prototype wi-fi earbud able to measuring physique temperature and taking an electrocardiogram (ECG) is one current instance of a wearable gadget being developed by ASE and one in every of its prospects (see figures 2).  Kueihao Tseng and colleagues at ASE highlighted the truth that the working electronics, packaging, and testing framework reside close to the skin of the earbud, with connections by means of pogo pins in a spherical PCB. This strategy improves sign integrity and allows part substitute. The engineers optimized the molding course of and metallic polymer materials for low resistance (<0.05Ωm), whereas remaining versatile for comfy match.
Fig. 2: The 3D SiP module on a versatile substrate connects the conductive electrode to temperature sensor to SiP module to spherical PCB on this good earbud. Supply: ASE
On the versatile printed circuit, a sign processing IC and passive parts convert mV-level biofeedback indicators to digital sign. The earbud measures temperature with a thermistor, which is inexpensive than an IR LED. With course of modifications, the ECG waveform was in a position to match the Apple watch benchmark (see determine 3).
Fig. 3: Electrocardiogram outcomes utilizing the prototype earbud correlate with the Apple watch benchmark. Supply: ASE
There are a number of foremost choices for connecting die bumps to substrate pads. Amongst them:
- Mass reflow is probably the most mature and least costly.
- Thermocompression bonding (TCB) makes use of drive and warmth and is suitable with low-k dielectrics, however it’s a lower-throughput course of.
- Laser-assisted bonding (LAB) gives localized heating in a shorter course of than TCB.
“For chiplet purposes, laser-assisted bonding works rather well, so long as the die dimension doesn’t get too massive,” mentioned ASE’s Chang. “For a lot bigger die, thermocompression bonding gives even heating and stress throughout the massive space.”
LAB was developed by Amkor engineers in 2014 and has been utilized in meeting strains since 2018 for flip-chip packaging. Amkor at present is growing a next-generation LAB know-how that particularly targets interconnection with thermal interface supplies (TIMs) in high-performance packages.
“Just lately, demand for fine-pitch flip chip bumps and enormous/skinny substrate packages has elevated, leading to trade curiosity in LAB as a consequence of its good high quality and excessive productiveness,” in response to SeokHo Na, director of Amkor Technology Korea.”  TIMs assist dissipate warmth from the die to lid in flip-chip BGAs utilizing conductive interfaces akin to gold. However the silicon die with a gold floor tends to mirror a lot of the laser directed at it, resulting in non-wet failures with conventional LAB.
The superior LAB course of as an alternative directs the laser on the bundle bottom by means of the instrument’s stage vacuum block. The engineers adjusted the method situations, together with energy and time of publicity, to type extra dependable copper pillar bumps with SnAg suggestions. Amkor famous that as compared with mass reflow, LAB is much less more likely to produce solder sidewall creep (wicking) and related to mass reflow and accommodates finer bump pitches. Different architectures, akin to 2.5D and 3D HBMs (in EMC), are more likely to reap the benefits of LAB, as properly. “Subsequent-gen LAB could be the solely resolution for fine-pitch bump units with bottom metallic (TIM) die,” concluded Na.
Embedded SiP is a quickly evolving market. In a just lately developed 3D embedded energy SiP, the molding compound (EMC) was the best concern. A characteristic of the platform is the EMC fill course of round energy FETs sandwiched between substrates.  The EMC needed to meet particular parameters of Younger’s modulus (stretch) and glass transition temperature (stream) to attenuate bundle warpage — particularly necessary in energy transistors as a result of they can not reap the advantages of Moore’s Legislation scaling. Warpage was simulated utilizing Ansys’ full finite ingredient mannequin software program.
Fig. 4: By switching from laminate substrate to leadframe-based processes with optimized thermocompression bonding and molding materials, a extra compact embedded SiP utilizing single-sided cooling is feasible. Supply: Amkor
Byron Jin Kim, senior director at Amkor Expertise Korea, and his workforce in contrast thermal outcomes utilizing ICEPAK software program for the embedded SiP with a dual-cooled IGBT on direct-bonded copper-on-ceramic substrate with three embedded constructions (see determine 4). The embedded technique of alternative (d) makes use of die connect on the underside substrate, and requires solely single-sided cooling. The workforce decided the leadframe-based course of module demonstrated superior thermal efficiency than the design with laminated substrates. As well as, the core ball placement is necessary.
“Cu core ball was carried out on high substrate by the method of flux printing-ball placement-reflow. This strategy was key to controlling correct solder wetting within the course of parameter set-up,” the report said. Going ahead, Amkor anticipates quite a lot of embedded SiP choices for related methods, together with energy circuits with half-bridge and full-bridge purposes.
Fig. 5: Thermocompression bonding course of exhibits die and copper ball placement (a), copper core ball wetting exhibits the routable Microleadframe at angle (b), and the bundle’s aspect view previous to molding (c). Supply: Amkor
Antenna in bundle
For 5G and 6G, antenna know-how is difficult. As an alternative of a single antenna, there are phased arrays of antennas, as a result of at mmWave and terahertz (THz) frequencies lengthy paths from semiconductor packages to antennas result in excessive losses. That makes it fascinating to combine these antennas into the SiP.
“Earlier than 2018, LGA SiPs have been used within the RF trade, however BGA has since been broadly adopted because of the event of double-sided packaging,” mentioned Yole’s Pereira. “Gamers like Broadcomm, Qorvo, and Skyworks implement stepwise improvements with options like DSBGA and DS-MBGA (double-sided molded BGA), whereas Murata immediately carried out DS-MBGA for system integration and miniaturization. The Built-in Fan-Out Antenna in Bundle (InFO_AiP) from TSMC is one other revolutionary resolution ready for use, however it has been delayed due to price inefficiency.”
Along with completely different bundle varieties, substrates for high-frequency makes use of are altering. Conventional PCB supplies can not meet the wants of 5G’s terahertz frequencies due to excessive dielectric loss and water absorption. The trade at present is evaluating numerous liquid crystal polymer (LCP) substrates for his or her electrical properties, hermeticity and materials flexibility.
“We’re all the time looking for the steadiness between sign power and sign loss, and so far as 5G, we’re taking a look at a number of completely different materials units, completely different LCP integrations,” mentioned Chang. “Hopefully that minimal loss resolution will simplify the general AiP design.”
Packaging homes and foundries are pursuing quite a lot of SiPs to satisfy the completely different wants amongst cellular shopper, communications and infrastructure, and automotive purposes. To cut back price and enhance manufacturing reliability, new supplies and processes are being added for flip chip, fan-out, and embedded SiPs. However the shifting goal related to sustaining sign integrity, transferring extra knowledge quicker, and overcoming tooling/substrate limitations will proceed to encourage next-gen innovation.
Fan-Out Packaging Gets Competitive
Manufacturability reaches enough degree to compete with flip-chip BGA and a pair of.5D.
Scaling, Advanced Packaging, Or Both
Variety of choices is rising, however so is the listing of tradeoffs.
System-In-Package Thrives In The Shadows
Multi-chip strategy cuts throughout all bundle varieties, dominates good telephone and wearables markets.
- Heyman, L. Peters, “Fan Out Packaging Will get Aggressive,” Semiconductor Engineering, Aug. 18, 2022, https://semiengineering.com/fan-out-packaging-gets-competitive/
- H. Na, et. al., “Subsequent Gen Laser Assisted Bonding (LAB) Expertise,” IEEE 72nd Digital Parts and Expertise Convention (ECTC), Might 2022,, pp. 1991-1995, doi: 10.1109/ECTC51906.2022.00313.
- Tseng, C.L. Lin, Ok. Wang, and H. Chang, “Good Biofeedback Earbud Achieved by SiP with 3D Composite Polymer Bundle,” ibid, pp. 786-793, doi: 10.1109/ECTC51906.2022.00130.
- J. Kim, et. al., “3D Embedded Energy Bundle Module to Combine Varied Energy Techniques,” ibid. pp. 289-295, doi: 10.1109/ECTC51906.2022.00054.</em>