With steady system scaling, course of home windows have change into narrower and narrower because of smaller function sizes and better course of step variability [1]. A key process throughout the R&D stage of semiconductor improvement is to decide on an excellent integration scheme with a comparatively massive course of window. When wafer check information is restricted, evaluating the method window for various integration schemes might be troublesome. To beat this limitation, we’ll talk about an instance of how digital fabrication can be utilized throughout course of window analysis of a DRAM capacitor patterning course of.

When creating a DRAM system, an array of holes used for capacitive cost storage have to be etched into the silicon wafer. The obtainable patterning schemes to fabricate a 40 nm gap array embody EUV LE, LE4, double SADP (80 nm mandrel pitch), and double SAQP (160 nm mandrel pitch). On this research, we chosen immersion double SADP and SAQP for our patterning schemes and in contrast the method sensitivity and course of home windows of our choices. A digital course of sequence (“circulation”) was constructed for every patterning scheme (SADP and SAQP) as proven in determine 1. We used the capacitor gap space as a metric for the capacitance and its uniformity evaluation. Construction search was utilized in SEMulator3D course of modeling to seek out the minimal and most capacitor gap space inside a 4×Four gap array, after which calculate the imply space, in order that the delta from most to minimal space may very well be calculated. Determine 2 shows the metrology outcomes for one output construction, with the minimal and most gap areas recognized.

Fig. 1: Main course of steps of SADP and SAQP.

Fig. 2: Digital metrology outcomes for minimal and most space.

Primarily based on this digital circulation and metrology, a Monte Carlo research with 3000 trials was carried out utilizing the SEMulator3D Analytics module. Mandrel CDs and spacer thicknesses had been chosen as Design of Experiment (DOE) enter parameters, whereas imply space and delta space had been chosen because the output parameters. Desk 1 lists the ranges of enter parameter values for the SADP and SAQP processes. The digital DOE outcomes guided our investigation relating to the influence of every enter on variations within the imply and delta space. In Desk 1, MX is the X path mandrel CD; MY, the Y path mandrel CD; SPX1, the X path 1st spacer thickness; SPX2, the X path 2nd spacer thickness; SPY1, the Y path 1st spacer thickness; and SPY2, the Y path 2nd spacer thickness.

Desk 1: DOE variables and enter ranges.

A bigger imply space and smaller delta are most well-liked for the next and extra uniform capacitance distribution. A imply space between 900 and 1100 nm2 and delta smaller than 200 nm2 had been outlined because the success standards that decided which trials handed or failed. The ratio of handed to failed simulation runs (often called the in-spec ratio) might be calculated for the method window below a selected set of situations, to generate a imply worth and 3-sigma (±3*customary deviation) distribution. This ratio signifies the fraction of enter combos that produce imply and delta areas inside the success standards ranges.

The in-spec ratio might be optimized by shifting the imply values of the enter course of parameters to be able to maximize the variety of profitable runs included within the imply±Three sigma window [2]. If the optimized in-spec ratio remains to be not excessive sufficient, specification (Three sigma) tightening can additional improve it. We calculated in-spec ratio for each SADP and SAQP processes below completely different situations. With the identical Three sigma distribution, the in-spec ratio of the SADP course of was about 10% greater than that of the SAQP course of. After the 3-sigma specification for the mandrel CD was modified, the in-spec ratio of the SADP course of was near 100%. The in-spec ratio was decrease for the SAQP course of on the similar mandrel CD, highlighting that the SAQP course of window wanted additional tightening.

On this research, digital fabrication was used to carry out course of window analysis and optimization for the capacitor formation course of in a sophisticated DRAM construction. The digital analysis supplied clear and quantified steerage to assist gauge course of difficulties on this superior DRAM construction utilizing completely different patterning schemes. Most significantly, we had been capable of decide optimum course of goal combos and the biggest allowable course of window for every patterning scheme, previous to wafer-based experimentation.

All for studying extra? Obtain the total white paper “Pathfinding By Process Window Modeling: Advanced DRAM Capacitor Patterning Process Window Evaluation Using Virtual Fabrication.”


  1. A.J., Strojwas, 2006 IEEE Worldwide Symposium on Semiconductor Manufacturing (pp. xxiii-xxxii).
  2. Q. Wang, Y. D. Chen, J. Huang, W. Liu and E. Joseph, 2020 China Semiconductor Expertise Worldwide Convention (CSTIC) (pp. 1-3).

Qingpeng Wang

Qingpeng Wang

  (all posts)

QingPeng Wang is a senior semiconductor course of and integration (SPI) engineer at Coventor, A Lam Analysis Firm. Previous to his place at Coventor, Wang labored in new know-how improvement at Semiconductor Manufacturing Worldwide Corp. (SMIC). He’s at the moment employed by Coventor’s SPI group in China, helping prospects with course of improvement and purposes engineering utilizing Coventor’s SEMulator3D product.

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