Lowering the parasitic capacitance between the gate steel and the supply/drain contact of a transistor can lower system switching delays. One strategy to cut back parasitic capacitance is to cut back the efficient dielectric fixed of the fabric layers between the gate and supply/drain. This may be executed by creating airgaps within the dielectric materials at that location. This sort of work has been executed up to now for back-end-of-line (BEOL) to cut back the capacitance between interconnects [1-4]. On this work, we give attention to the front-end-of-line (FEOL) and exhibit a SEMulator3D mannequin of an airgap created between the gate and supply/drain [5]. SEMulator3D is a digital fabrication software program platform that may mannequin course of variability inside a given semiconductor course of stream. Utilizing the Design of Experiment (DoE) capabilities within the SEMulator3D device, we present the dependence of the parasitic capacitance on the etch depth and different etch course of parameters used to create the airgap. Moreover, we present the dependence on the scale and quantity of the airgap.

Determine 1 shows a cross-section view of a SEMulator3D FinFET mannequin. To create an airgap between the gate and the supply/drain of the FinFET,  a extremely selective silicon nitride etch course of is carried out, adopted by a silicon nitride deposition course of which is optimized to pinch off and create the airgap. A silicon nitride CMP course of is then used to planarize the floor.

Fig. 1: SEMulator3D course of stream for creating an airgap in a FinFET mannequin. The visibility deposit step creates the airgap by pinching off the airgap on the prime. The CMP step is then used to take away the surplus nitride. Scale bar is 10nm. The airgap reduces the parasitic capacitance between gate and supply/drain. The scale of the airgap might be managed by various the etch depth, tilt and supply sigma of the etching reagents.

Utilizing SEMulator3D’s digital metrology capabilities, the next metrics have been then measured:

  • Parasitic capacitance between the gate steel and S/D contact
  • Quantity of the airgap
  • Z-axis minimal of the airgap which is consultant of the vertical dimension of the airgap

Throughout the silicon nitride etch step, the etch depth, the angular unfold of the etching reagents (known as supply sigma within the literature) and the lean angle (with the wafer assumed to be rotating) have been different through the DoE. Determine 2(a-f) present how the capacitance and quantity of the airgap different with the etch depth for various values of tilt and supply sigma. Because the etch depth is elevated, we create a bigger airgap (determine 2 d). This decreases the efficient dielectric fixed since air’s dielectric fixed is way decrease than that of the nitride. This in flip, reduces the parasitic capacitance between the gate and supply/drain. A lower within the tilt angle has the impact of shifting the etching reagents away from the facet partitions and in direction of the underside of the ensuing airgap (determine Three b-c). This explains the bigger airgap (and decrease capacitance) for a given depth and supply sigma, as we lower the lean (determine 2 a & d). One other important result’s that because the supply sigma will increase, the impact of tilt decreases. When the supply sigma is ready at 5, akin to a broad/isotropic angular unfold, tilt has no impact in any respect on the capacitance and airgap quantity (determine 2 c & f). That is in line with the how growing supply sigma impacts etching. Rising the supply sigma makes the etching reagents hit the substrate in a extra isotropic method (determine Three a). Which means the lean now not impacts the etching conduct because it does at decrease supply sigma values.

Fig. 2: Because the etch depth is elevated, airgap quantity will increase and the parasitic capacitance decreases (determine 2 a & d). This lower is steeper when the lean angle is decrease. Nonetheless, the impact of tilt decreases because the supply sigma is elevated. When supply sigma is 5, tilt has no impact on the capacitance and airgap quantity (determine 2 c & f).

Fig. 3: (a) Impact of Angular Unfold (Sigma) on the directionality of the etching reagents (b) Impact of a tilt of 45 levels proven (wafer fastened) (c) Impact of a tilt of 80 levels (wafer rotating). Picture supply: SEMulator3D product documentation

Working a big DoE is a time and computational useful resource intensive course of. Whereas it’s mandatory to do that for course of optimization, any discount within the parameter area of the DoE helps cut back the time and assets wanted. A machine studying mannequin that may predict outcomes primarily based on impartial variables is beneficial because it reduces the necessity for working the DoE for all combos of the impartial variables. With this purpose in thoughts, the info collected on this DoE was fed into a synthetic neural community (ANN) after splitting the info into coaching (70%) and testing (30%) units. The mannequin had two hidden layers (determine Four a). The grid search methodology was used for hyper parameter tuning. The mannequin was run on the check knowledge and located to have a imply accuracy of 99.8%. Three quarter of check circumstances had an absolute % error (APE) of 0.278% or decrease (determine Four c). Determine Four e shows a pattern of check rows with the expected and precise parasitic capacitance. This utility of machine studying (ML) permits us to cut back the scale and time wanted for the DoE. We will cut back the parameter area considerably with out decreasing the accuracy of the outcomes considerably. In our case, the DoE dimension was diminished from ~5000 to ~2000 parameter combos. SEMulator3D’s customized python step integrates such a machine studying code into the method simulation, and the outcomes might be fed to the subsequent step within the semiconductor course of mannequin.

Fig. 4: An Synthetic Neural Community (ANN) mannequin to foretell the parasitic capacitance primarily based on the etch depth, tilt and supply sigma. The prediction accuracy on the check knowledge was discovered to be 99.8%. The metric to measure the distinction between the expected capacitance and the precise capacitance was absolute % error (APE). 75% % of check circumstances had an APE of 0.28% or decrease. An correct machine studying mannequin permits a smaller parameter area to be explored and therefore decrease time and computational assets.

Conclusions

Coventor SEMulator3D was used to create a digital airgap between the gate and the supply/drain of a FinFET system. The influence of this airgap on parasitic capacitance was studied. Etch course of parameters have been different and the influence on the airgap quantity and parasitic capacitance was additionally studied. The outcomes have been fed into a synthetic neural community to create a machine studying mannequin that may predict parasitic capacitance, thereby decreasing the necessity to run a DoE for each mixture of etch parameter values.

References

[1] Hargrove, M. (2017, October 18). Lowering BEOL Parasitic Capacitance utilizing Air Gaps https://www.coventor.com/blog/reducing-beol-parasitic-capacitance-using-air-gaps

[2] Nitta, S., Edelstein, D., Ponoth, S., Clevenger, L., Liu, X., & Standaert, T. (2008, June). Efficiency and reliability of airgaps for superior BEOL interconnects. In 2008 Worldwide Interconnect Expertise Convention (pp. 191-192). IEEE.

[3] Shieh, B., Saraswat, Ok. C., McVittie, J. P., Checklist, S., Nag, S., Islamraja, M., & Havemann, R. H. (1998). Air-gap formation throughout IMD deposition to decrease interconnect capacitance. IEEE Electron System Letters, 19(1), 16-18.

[4] Fischer, Ok., Agostinelli, M., Allen, C., Bahr, D., Bost, M., Charvat, P., … & Natarajan, S. (2015, Could). Low-k interconnect stack with multi-layer air hole and tri-metal-insulator-metal capacitors for 14nm excessive quantity manufacturing. In 2015 IEEE Worldwide Interconnect Expertise Convention and 2015 IEEE Supplies for Superior Metallization Convention (IITC/MAM) (pp. 5-8). IEEE.

[5] Banna, S. (2016, August). Scaling challenges and options past 10nm. In 2016 IEEE Worldwide Convention on Electron Gadgets and Strong-State Circuits (EDSSC) (pp. 181-186). IEEE.

Sumant Sarkar

  (all posts)

Sumant Sarkar is a semiconductor course of and integration (SPI) engineer at Lam Analysis. He has 18 years of expertise within the software program and analytics business, together with positions at Oracle and nanobi analytics from 1997 to 2015, after which he went again to graduate faculty. Sarkar joined Lam Analysis in March 2022, and is at present working for Lam’s SPI group in North America, the place he’s chargeable for superior nanotechnology improvement and course of modeling initiatives with Lam’s key companions and prospects. He obtained a bachelor’s diploma in EE from IIT Kharagpur, grasp’s diploma in Nanotechnology from IISc Bengaluru, and a Ph.D. in Physics & Supplies Science from Northern Arizona College, the place he developed strategies for reaching robust and controllable round dichroism at ultraviolet wavelengths.



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