One of many key applied sciences to allow scaling under 3nm entails delivering of energy on the bottom of a chip. This novel method enhances sign integrity and reduces routing congestion, but it surely additionally creates some new challenges for which right now there are not any easy options.

Bottom energy supply (BPD) eliminates the necessity to share interconnect assets between sign and energy strains on the wafer frontside. As an alternative, because the title implies, energy is moved to the again of the wafer so solely indicators are carried by frontside interconnects. Intel, Samsung and TSMC all have introduced plans to implement BPD in some kind at across the 2nm node.

Along with relieving the RC bottleneck, BPD allows value financial savings. “Bottom energy supply removes the necessity for an influence supply monitor from decrease layer front-side interconnects,” mentioned Sanjay Natarajan, senior vp and co-general supervisor for Logic Expertise Improvement at Intel. “Intel then has the choice to be much less aggressive on interconnect scaling with out skipping a beat on transistor density scaling. This enables for much less advanced and finally cheaper decrease layer steel patterning.”

Fig. 1: Interconnect levels on traditional logic device (left) and backside power distribution network with PowerVia (right). Source: Intel

Fig. 1: Interconnect ranges on conventional logic system (left) and bottom energy distribution community with PowerVia (proper). Supply: Intel

It additionally permits these totally different steel layers to be optimally fabricated — as wider strains for Vdd and Vss, and thinner strains to hold indicators. Nonetheless, a bottom energy community introduces substantial wafer processing challenges — particularly because the change can happen on the similar node because the system maker’s swap from finFETs to nanosheet transistors.

As an illustration, Intel will introduce RibbonFET and PowerVia at its 20A (2nm) node “The primary key problem round PowerVia entails patterning {an electrical} contact function throughout the tight areas round next-generation RibbonFET transistors with out impacting their efficiency. The second is thinning the bottom silicon to ship as direct and as low resistance a connection as doable in a repeatable and controllable method,” mentioned Natarajan.

As a result of BPD approaches are so new, the business is weighing the professionals and cons to totally different architectures.

Fig. 2: BPD schemes afford different scaling benefits associated with increasing levels of wafer processing complexity. Source: Applied Materials

Fig. 2: BPD schemes afford totally different scaling advantages related to rising ranges of wafer processing complexity. Supply: Utilized Supplies

BPD schemes
The perfect energy supply community delivers fixed, steady provide voltage to energetic circuits on the IC throughout any exercise. “The important thing parameter is the DC resistance of the PDN in all of the interconnect paths, from the facility provide pins of the IC to the transistors within the circuits.” [1]

Determine 2 exhibits three implementations of bottom energy supply networks. “Within the first method, the logic cells retain an influence rail, and the bottom energy distribution community is related to the facility rail by a nano TSV,” mentioned Mehul Naik, managing director at Utilized Supplies. “Within the second method, there isn’t any energy rail within the logic cell. As an alternative, an influence through straight transfers energy from the bottom community to the cell or the transistor contact. This method is extra advanced, but it surely improves energy effectivity and will increase cell space scaling. Within the third method, energy from the bottom community is related straight to every transistor’s supply and drain.”

Imec was one of many first to develop a bottom energy supply method and it makes use of what it calls buried energy rails (BPRs). “If we do bottom energy supply community, and likewise for the buried energy rail, there’s a through from the supply/drain areas, from M0 to that BPR. So now we have TSVs going by means of the silicon and touchdown on the buried energy rail, however the buried energy rail is made even earlier than the transistors are made. It sits in between what would be the nanosheet fins earlier than the gate is shaped and earlier than the supply/drain epi is completed,” defined Eric Beyne, senior fellow, vp of R&D, and director of the 3D System Integration Program at imec. “That’s one purpose why copper won’t ever be used for this. It has to undergo all of the front-end processing, so it must be suitable — one thing like tungsten or molybdenum, or perhaps ruthenium.”

Constructing these into the manufacturing move is a problem by itself. “These energy rails are made at a second of time of the method the place you’ve your fins or sheets outlined, the place the house between these fins is at its largest, as a result of when you deposit the gate-all-around and the steel, the fin is thicker and the spacing between two neighboring fins could be very slim,” Beyne mentioned. “So then it’s important to make the through very deep with an excellent smaller function measurement.”

He famous that the brief through to the bottom energy rail might be located at tight areas alongside the BPR, offering a superb efficiency profit.

The BPR runs parallel to the fin route, and it’s buried partially within the shallow trench isolation and partially within the silicon substrate. That is totally different from a standard energy grid with energy rails in M0 or M1, and it allows commonplace cell peak discount.

“Intel’s PowerVia gives a extra direct, single-feature connection between the bottom energy supply community and a standard supply contact, that we consider can obtain a lot decrease resistances in comparison with the imec method,” mentioned Natarajan.

Fig. 3: The power delivery network design margin permits 10% IR drop. Higher levels can threaten device performance. Source: Applied Materials

Fig. 3: The facility supply community design margin permits 10% IR drop. Increased ranges can threaten system efficiency. Supply: Utilized Supplies

Fig. 4: By moving the power rail, the standard cell area can be scaled by 20% to 30%. Source: Applied Materials

Fig. 4: By shifting the facility rail, the usual cell space might be scaled by 20% to 30%. Supply: Utilized Supplies

Why bottom energy, and why now?
The explanation for making this substantial change to the best way energy is delivered to transistors has to do with the voltage (IR) penalty, whereby electrons should journey by means of 15 or extra layers of interconnect strains and vias on their option to delivering energy and information to billions of transistors in a contemporary SoC. [2]  Energy effectivity can attain specification limits of 90%, or 10% voltage (IR) loss between the chip’s voltage regulator and its transistors.

In bottom energy supply, the facility rails are moved outdoors of the logic cells, enabling logic density enhancements, which Utilized Supplies estimates to be equal to as a lot as two generations of lithography scaling (see determine 2). As a result of the facility is delivered straight from under the transistors, the IR drop is drastically decreased.

Simulation and fabrication research carried out by Arm and imec decided that bottom energy supply might be 7X as environment friendly as a frontside energy supply community, supplied the nanoTSVs might be positioned nearer than 2µm from one another. [2]

However a number of course of and supplies adjustments have to be realized to make BPD a actuality in manufacturing fabs. “For higher space utilization and efficiency enhancement, bottom energy supply (BPD) community is a beautiful choice. For its enablement, steady course of and power development is important not solely on movie, etch, lithography and moist, but additionally on wafer bonding and thinning applied sciences,” said Tomonari Yamamoto, vp of system know-how, Company Innovation Division at TEL.[3] Certainly, plenty of decrease resistance metals are being evaluated as potential candidates for changing copper, which might be mandatory as BEOL interconnect CDs delve under 15nm.

Fig. 5: The backside power delivery network flow requires extreme wafer thinning to <500nm atop a 50nm SiGe layer with 350nm silicon epi cap. Buried power rails of ruthenium feature 40% lower resistance than tungsten rails. Wafer-wafer bonding is followed by thinning, CMP, dry and wet etch, then TSV and M1 formation. Source: imec

Fig. 5: The bottom energy supply community move requires excessive wafer thinning to <500nm atop a 50nm SiGe layer with 350nm silicon epi cap. Buried energy rails of ruthenium function 40% decrease resistance than tungsten rails. Wafer-wafer bonding is adopted by thinning, CMP, dry and moist etch, then TSV and M1 formation. Supply: imec

Buried energy rails and BPD
The imec course of move (see determine 5) begins with epitaxial development of SiGe after which a silicon cap layer. A excessive Ge focus (25%) allows larger selectivity to CMP cease on the movie. The lengthy buried energy rails are then etched in STI and prolong into the silicon. Imec in contrast tungsten and ruthenium CVD movies, the latter of which supplied 40% decrease resistance. The wafer is then completely bonded to a provider wafer utilizing SiCN-SiCN dielectric bonding. Then the wafer undergoes backgrinding and CMP, then dry and moist etch. The SiGe is eliminated by chemical etch.

The wafer bonding course of have to be carried out fastidiously to reduce distortion, which interferes with subsequent patterning steps. “While you do the bonding, there’s a important risk of distortion within the sample after bonding, and the bottom patterning has to right for these distortions,” mentioned Beyne. “It might not be a lot, however even at 1ppm of scaling, which isn’t even 1°C in temperature, you increase the silicon and might find yourself with 150nm of misalignment on the wafer edges.”

Subsequent, the nanoTSV course of begins with oxide deposition (LPCVD) adopted by self-aligned DUV patterning. Utilizing superior lithography correction strategies, overlay of 100nm in x and y instructions was decreased to 10nm. A Bosch etch device creates the excessive AR nanoTSVs, touchdown on the BPR oxide and STI. Subsequent, PECVD oxide was deposited contained in the nanoTSV, adopted by sputter etching of the BPR for good contact between the nanoTSVs and BPRs. TiN ALD is adopted by W CVD and W CMP. Then copper damascene types the bottom steel.

Fig. 6: TEM cross section of passive test structure shows backside copper with 90nm nanoTSVs landing on buried power rails. Source: imec

Fig. 6: TEM cross part of passive check construction exhibits bottom copper with 90nm nanoTSVs touchdown on buried energy rails. Supply: imec

Beyne mentioned different troublesome challenges contain bottom patterning and exactly lining up the facility rails and the usual cell dimensions. Whereas state-of-the-art overlay tolerance is round 3nm with EUV lithography, on the wafer bottom with the distortion points related to wafer bonding, the overlay tolerance vary is ~20nm.

“After all, you’ve all the standard challenges with interconnect processing, creating excessive side ratio dimensions, depositing skinny liners and limitations with out voids, and many others.,” he mentioned.

Importantly, if the transistors are processed first, as happens in all wafer fabs right now, then new interconnect metals won’t essentially should be adopted on the 2nm node. Certainly, it seems that Intel’s PowerVia permits simply that. “We’ve designed our PowerVia course of to be suitable with each conventional front-end contact metals (together with tungsten) and superior steel processes to get the perfect efficiency out of PowerVia,” mentioned Natarajan.

Naik described bottom energy supply community as a type of design-technology co-optimization (DTCO), the place design and course of innovation ship system degree advantages. He highlighted the thermal constraint that exists when the bottom nanoTSVs are being constructed.

“We have to engineer the bottom contact to the transistor supply to have the bottom doable resistance,” Naik mentioned. “This usually requires excessive temperature epi and anneal processes. Nevertheless, as a result of the bottom contacts are being manufactured with the front-side transistors and interconnects in place, they’d be degraded by these excessive temperatures. To handle this, Utilized is creating a low-temperature resolution that mixes as much as seven steps in excessive vacuum, together with chambers for preclean, selective silicide deposition, ALD or PVD liner deposition, and a brand new steel fill. A co-optimized CMP step leaves a superbly uniformed bottom contact layer, on which we are able to construct a copper bottom energy distribution community.”

Offering deposited movies that adequately isolate transistors from the facility community together with etch steps that method the transistor’s energetic space would require exact engineering. “In etch, you need excessive anisotropy, defect-free and damage-free outcomes, no matter which of the course of move,” mentioned David Fried, vp of computational merchandise at Lam Research. “In deposition, it’s all concerning the materials parameters that you just’re attempting to deposit. You need low defectivity, excessive throughput, and the power to engineer these supplies.”

As soon as firms do make the transition to bottom energy supply networks, it’s vital that the method is scalable to the subsequent course of node, as properly. “Our commonplace cell pitch is 105nm, and in the event you join the nanoTSV to each different buried energy rail, there’s a connection each 210nm — so 200nm strains and 200nm spacing. That is decoupled from the usual cells, in order that in the event you scale then to 80nm, it nonetheless works and also you don’t should do EUV lithography on the bottom, on this case,” Beyne mentioned.

Subsequent steps in minimizing RC delay
Since across the 22nm system era, BEOL RC delay has made up a larger portion of complete system delay as transistors proceed scaling. For copper damascene approaches, void-free copper fill turns into increasingly more difficult, and ultrathin wetting and capping CVD course of development are required.

“With copper, we are able to go all the way down to one thing like 200nm, however you want a copper seed layer for electroplating. For nanoTSVs, tungsten and different metals scale higher in excessive side ratio buildings, utilizing ALD and CVD supplies, however you continue to want a TiN barrier steel for tungsten, as an example. In some unspecified time in the future, you’ve extra barrier than bulk steel, like at 30nm dimensions,” mentioned Beyne. “Molybdenum could be very enticing for a few of these TSV purposes as a result of it’s ALD and it deposits straight on the floor. I might say tungsten is the most typical materials of right now. Choices for enchancment embrace ruthenium and molybdenum, however they’re nonetheless within the analysis section.”

TEL’s Yamamoto had an analogous view. “Ruthenium is a candidate since it’s much less delicate to scattering and doesn’t want thick barrier steel, however simply wants an adhesion layer with lower than 1nm thickness.” He added that damascene flows have a tendency to supply side ratio of two, whereas subtractive etch schemes allow increased side ratio, which would cut back resistance, whereas the capacitance enhance might be managed, as an example, by changing low-k movies with air gaps.

Conclusion
Optimizing interconnect efficiency for a bottom community is considerably just like that of the frontside — guaranteeing low resistance and long-term reliability for the bottom metals. Natarajan notes, nevertheless, that by segregating energy routing on the bottom steel stack from sign routing on the frontside steel stack, engineers have the liberty to optimize resistance versus capacitance independently. Corporations may additionally make totally different architectural decisions, corresponding to twin damascene versus subtractive processes (steel deposition and etch), relying on efficiency wants.

The main system producers might be incorporating bottom energy supply in 2nm designs, guaranteeing cleaner energy supply and breaking apart the RC bottleneck. A mix of advances in deposition, etch, CMP, bonding, wafer thinning, and DTCO will influence this inflection level.

References

  1. Jourdain, M. Stucchi, G. Van der Plas, G. Beyer, E. Beyne, “Buried Energy Rails and Nano-Scale TSV: Expertise Boosters for Bottom Energy Supply Community and 3D Heterogenous Integration,” 2022 IEEE 72nd Digital Parts and Expertise Convention, doi: 10.1109/ECTC51906.2022.00244.
  2. Cline, D. Presaderic, E. Beyne, O. Zografos, “Subsequent-Gen Chips Will Be Powered from Under,” IEEE Spectrum, 26 Aug. 2021, https://spectrum.ieee.org/next-gen-chips-will-be-powered-from-below.
  3. Yamamoto, “Superior Course of Applied sciences for Steady Logic Scaling In the direction of 2nm and Past,” 2022 IEEE Worldwide Interconnect Expertise Convention, June 27-30, 2022, doi: 10.1109/IITC52079.2022.9881297.



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