FPGA design developments; silicon photonics; RISC historical past; adaptive headlights.


Siemens EDA’s Harry Foster examines developments associated to numerous facets of FPGA design and the rising design complexity related to rising variety of embedded processor cores, asynchronous clock domains, and extra security options.

Synopsys’ Twan Korthorst and Kenneth Larsen take a broad take a look at silicon photonics, together with the advantages of digital integration, accelerating the event of photonic IC designs throughout markets, and why firms are enthusiastic about shifting to built-in lasers.

Cadence’s Paul McLellan seems to be again on the early historical past of RISC processors and the event of the IBM 801, which was initially designed to run a phone swap.

Ansys’ Emmanuel Follin checks out how adaptive headlights modify their beam sample in response to driving circumstances and among the challenges and designing and testing them.

In a podcast, Arm’s Geof Wheelwright chats with Mark Hambleton about what ‘software program outlined’ means and the advantages it might have for builders, shoppers, and the broader tech trade.

Riscure’s Jasper van Woudenberg checks out an effort to find out whether or not Starlink person terminals are immune to fault injection assaults.

Renesas’ Roger Wendelken notes the significance of teaching prospects on the necessity for safety, the best way to handle safety layers, and understanding the restrictions of a tool.

In a weblog for SEMI, ASM Worldwide’s John Golightly argues that firms within the semiconductor worth chain ought to participate in efforts to hurry sustainability improvements, develop and undertake requirements and processes, demystify present schemes for calculating carbon emissions reductions, and share methods to satisfy carbon emissions disclosure necessities.

Plus, try the blogs featured within the newest Low Power-High Performance newsletter:

Cadence’s Tom Beckley examines what is required to succeed with system-in-package.

Synopsys’ Manoz Palaparthi exhibits the best way to ferret out the foundation causes of early full-chip LVS sooner.

Siemens’ Janet Attar presents a case research in low-power and high-performance AI processors.

Arm’s Jack Melling exhibits how a scarcity of {hardware} and firmware standardization between SoCs can hinder the deployment of edge computing functions.

Keysight’s Don Dingee finds that workflows are altering, and design can now not be an remoted exercise.

Cycuity’s Jim Robinson places ahead 4 ranges to evaluate present capabilities and take steps in direction of end-to-end {hardware} safety verification.

Jesse Allen

Jesse Allen

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Jesse Allen is the Information Heart administrator and a senior editor at Semiconductor Engineering.

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