Electrostatic discharge (ESD) points in built-in circuit (IC) chip designs have turn into extra crucial at superior semiconductor course of nodes, as a result of shrinking transistor dimensions and oxide layer thickness [1]. There are various ESD design guidelines and flows that designers examine for frequent ESD points, comparable to topological checks for the existence of ESD safety units, present density (CD) checks on the robustness of ESD discharge paths, and point-to-point (P2P) resistance checks to make sure the resistances from chip-level bumps to ESD safety units are under sure design thresholds [2-3]. Nevertheless, most ESD design guidelines out there to IC chip designers don’t appear to have in mind the truth that an ESD safety gadget should function inside the boundary of its ESD design window. Likewise, many designers don’t perceive the affect a poorly-designed ESD design window can have on their designs.

ESD design home windows

An ESD design window defines the voltage and present limits inside which an ESD safety gadget operates throughout an ESD occasion. Determine 1 illustrates a typical ESD design window:

  • VDD is the traditional working voltage of the circuitry
  • Vt2 and It2 are the voltage and electrical present, respectively, at which the ESD safety gadget will fail or break down to guard the sufferer circuitry.

Fig. 1: ESD design window.

On the precise aspect of the ESD design window, because the voltage will increase and reaches the area of circuitry breakdown voltage, the sufferer circuitry will likely be broken. An ESD design window defines the voltage and electrical present working area for the ESD safety gadget. Ideally, an ESD safety gadget is triggered or turned on at a voltage that’s someplace above the traditional circuitry working voltage, however will fail or break down when it reaches a voltage that’s someplace under the breakdown voltage of the sufferer circuitry.

If an ESD safety gadget is just not correctly designed such that it’s not triggered or turned on earlier than the sufferer circuitry reaches its breakdown voltage, the sufferer circuitry will break down earlier than the ESD safety gadget has an opportunity to truly present safety. Understanding the ESD design window of your ESD safety gadget is essential to make sure that its higher voltage boundary doesn’t attain or exceed the breakdown voltage of the sufferer circuitry.

At superior semiconductor course of nodes, circuitry working voltages have decreased, as has the breakdown voltage of gate oxide for the method node. Nevertheless, the breakdown voltage of gate oxide has decreased sooner than the circuitry working voltage, leading to a smaller voltage vary for ESD design home windows at smaller course of nodes [4-5]. This dichotomy makes it crucial and difficult to rigorously plan the working voltage and electrical present of the ESD safety gadget to make sure that ESD safety units function inside their ESD design home windows.

Estimating breakdown voltage

The circuitry working voltage (VDD in determine 1) is normally identified to designers. After they choose the sort and measurement of an ESD safety gadget, in addition they know the working and failing voltages and electrical present limits (comparable to Vt2 and It2 in determine 1) of the ESD safety gadget. The lacking half is the willpower of the higher voltage boundary of the ESD design window, which is proscribed by the breakdown voltage of the sufferer circuitry. This voltage is just not an actual calculation—designers derive an estimated voltage primarily based on the breakdown voltage of the sufferer circuitry. Nevertheless, if the sufferer gadget (the gadget instantly linked to the ESD safety gadget) is just not instantly linked to the bottom (i.e., if there are a number of different units linked in collection between the sufferer gadget and the bottom), utilizing the breakdown voltage of the sufferer gadget alone because the breakdown voltage of the sufferer circuitry could also be overly pessimistic, and the ESD safety gadget will fail or break down too quickly. However, designers don’t wish to over-estimate the breakdown voltage of the sufferer circuitry, such that the working and failing voltages and electrical present limits of the ESD safety gadget prolong into the area of the sufferer circuitry breakdown voltage, as this can end result within the sufferer circuitry being broken earlier than the ESD safety gadget fails or breaks down.

To correctly outline the higher voltage boundary of an ESD design window, some IC chip designers use the next technique to find out the breakdown voltage of the sufferer circuitry, as proven in determine 2:

  • First look at all attainable electrical paths between the sufferer gadget and the bottom,
  • Add up the breakdown voltages of all gadget junctions on every path,
  • Discover the trail with the bottom complete breakdown voltage, and
  • Use this lowest complete breakdown voltage because the breakdown voltage of the sufferer circuitry.

Fig. 2: Guide identification and calculation of the bottom complete breakdown voltage examines all attainable electrical paths between a sufferer gadget and the bottom.

The necessity to correctly decide the higher voltage boundary of an ESD design window exists in each situation the place an ESD safety gadget is used. Relying on the place within the circuitry an ESD safety gadget is positioned, an IC designer may have to search out out the bottom complete breakdown voltage for electrical paths between:

  • A sign bump and an influence or floor bump,
  • An influence bump and a floor bump, and
  • A sufferer gadget and an influence or floor bump, and so on.

In a fancy IC chip design, it’s nearly unimaginable to manually look at all attainable electrical paths, add up the breakdown voltages of all gadget junctions on every path, and establish the trail with the bottom complete breakdown voltage. Fortuitously, there are digital design automation instruments that may assist design groups precisely establish the bottom complete breakdown voltage for any electrical path, regardless of how advanced. With this information, designers can estimate probably the most acceptable higher voltage boundary for the ESD design window.

We’ll take a look at how the method works utilizing the Calibre PERC reliability verification platform from Siemens EDA.

Automated breakdown voltage calculation

The Calibre PERC reliability verification platform permits designers to write down rule-based flows for checking advanced ESD issues in IC chip designs on the mental property (IP), block, and full-chip ranges. We start by writing a Calibre PERC move that may analyze a netlist and output the trail with the bottom complete breakdown voltage between two given pins.

The Calibre PERC move accepts both a structure database (GDSII or OASIS) or a schematic netlist (SPICE) as enter. If utilizing a structure as enter, the Calibre PERC platform first runs a structure vs. schematic (LVS) extraction to generate an electrically-equivalent structure netlist from the structure database. Beginning with the SPICE netlist or the generated structure netlist, the Calibre PERC platform traverses the whole hierarchy of the netlist to establish all attainable electrical paths between two given pins. For every electrical path, the Calibre PERC platform identifies all gadget junctions on the trail. Based mostly on an enter file containing a desk of gadget names and breakdown voltages of gadget junctions, the Calibre PERC platform calculates the full breakdown voltage of all gadget junctions on every path. Lastly, the move outputs the trail (together with all units on the trail) with the bottom complete breakdown voltage, in addition to the worth of the bottom complete breakdown voltage. Determine Three illustrates this move beginning with the structure database.

Fig. 3: The Calibre PERC move calculates the bottom complete breakdown voltage between two given pins.

Designers can then evaluation the output outcomes of this move within the Calibre RVE outcomes viewer, and the Calibre DESIGNrev structure viewer to see a visible illustration of {the electrical} path with the bottom complete breakdown voltage in a schematic or structure view. Determine 4a exhibits the outcomes of {the electrical} path with the bottom complete breakdown voltage, with all gadget names on the trail, whereas 4b is the schematic view of the 2 given pins and all units on {the electrical} path with the bottom complete breakdown voltage. This path with the bottom complete breakdown voltage can be the weakest path between the 2 given pins.

Fig. 4: (a) Calibre RVE outcomes displaying the units on {the electrical} path between two given pins FG and VSS, which is the trail (from FG to VSS) with the bottom complete breakdown voltage, (b) Calibre RVE schematic view of the 2 pins and the units on the trail.

Understanding the bottom complete breakdown voltage might help IC chip designers extra precisely estimate the higher voltage boundary of ESD design window, guaranteeing that ESD safety gadget operation is optimized whereas offering full safety to the sufferer circuitry.

Abstract

Assembly ESD design safety necessities is a crucial a part of at this time’s IC chip designs. Automated EDA flows that examine for some frequent ESD points, such because the connectivity to ESD units or the robustness of ESD discharge paths, are available to IC chip designers, both via foundry-supported PDKs or customized rule decks. Nevertheless, designers are sometimes unaware of automated EDA flows that may assist IC chip designers calculate the breakdown voltage of sufferer circuitry, which might help them extra exactly outline the higher voltage restrict of an ESD design window. Utilizing a instrument just like the Calibre PERC platform permits designers to rapidly and precisely establish {the electrical} path between two given pins with the bottom complete breakdown voltage. This lowest complete breakdown voltage can be utilized to extra precisely estimate the higher voltage restrict of an ESD design window, guaranteeing ample ESD safety for design circuitry.

For extra data, learn the technical paper A better way to estimate breakdown voltage for ESD design windows on Siemens EDA.

References

  1. A. Ille et al., “Reliability points of gate oxide underneath ESD pulse stress,” 2007 29th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2007, pp. 6A.1-1-6A.1-10, doi: 10.1109/EOSESD.2007.4401771
  2. EDA Software Working Group (ESD Affiliation), “ESD Affiliation Technical Report for ESD Digital Design Automation Checks”, ESD TR18.0-01-14. https://www.esda.org/store/standards/product/4/esd-tr18-0-01-14
  3. D. Yan, “Making certain Sturdy ESD Safety in IC Designs,” Siemens Digital Industries Software program, 2017. https://resources.sw.siemens.com/en-US/white-paper-ensuring-robust-esd-protection-in-ic-designs
  4. O. Semenov, H. Sarbishaei, and M. Sachdev, “ESD Safety System and Circuit Design for Superior CMOS Applied sciences,” Springer Science, 2010. P. 14. https://link.springer.com/book/10.1007/978-1-4020-8301-3
  5. A. Dong, J. Xiong, S. Mitra, W. Liang, R. Gauthier Jr., and A. Loiseau, “Complete Research of ESD Design Window Scaling All the way down to 7nm Expertise Node”, 2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 23-28 September 2018. https://ieeexplore.ieee.org/document/8509689.

Derong Yan

Derong Yan

  (all posts)

Derong Yan is a principal product engineer within the Calibre Design Options Division of Siemens EDA, part of Siemens Digital Industries Options. His main focus is the Calibre PERC reliability platform and reliability verification technique. Areas of experience embody SoC bodily design and verification, reliability verification, and design automation. Earlier than becoming a member of Siemens, Yan labored for a number of semiconductor corporations. He holds a Ph.D. in Supplies Engineering from the College of Alberta and obtained each his M.Sc. and B.Sc. from Shanghai Jiao Tong College.



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